Despite the performance gains available through differential signaling, the cost of two conductors per signal continues to impede its adoption in a number of chip-to-chip signaling applications, particularly those that require relatively wide data paths (e.g., between a memory controller and memory devices). Instead, single-ended signaling continues to prevail in such applications.
FIG. 1 illustrates a number of performance-limiting characteristics of a conventional single-ended signaling system. As shown, the system includes a signal-transmitting integrated circuit (IC) 101 and counterpart signal-receiving IC 103 coupled to one another via a single-ended signaling link 105 and powered by a DC power supply 104. The transmitting IC 101 includes an output driver 106 to modulate the potential on signal line 105 in accordance with a stream of transmit data bits (i.e., TxD, the data to be transmitted) and thus deliver a corresponding stream of symbols to the receiving IC 103. The receiving IC includes a signal receiver 115 to compare the signal line potential (VSIG) with a reference voltage (VREF) and to sample the comparison result at regular intervals, thereby recovering the data bit (i.e., logic ‘1’ or ‘0’) conveyed in each transmitted symbol.
With regard to performance limitations, if VREF is not centered between the logic ‘1’ and logic ‘0’ levels of the incoming signal (i.e., between VHI and VLO), the minimum difference between VREF and VSIG is compressed, thus rendering the incoming signal more susceptible to noise-induced error (i.e., the signaling margin, or noise tolerance, is reduced). Such an error is illustrated in FIG. 1 by the noise-induced crossing of the VREF level shown at 112.
Another challenge presented within the single-ended signaling system is the data-dependent current draw from the power supply 104. That is, when a logic ‘1’ is transmitted, a DC current is pulled through the impedance network (i.e., modeled by transmit-side pull-up impedance, ZT, the signaling line impedance, Z0, and receive-side pull-up impedance, ZR) to discharge the signal line 105, while no such DC current is drawn during transmission of a logic ‘0’ (thus permitting the signal line to charge toward VDD). This data-dependent switching of the DC current through inductive components of the impedance network generates supply voltage noise that tends to couple asymmetrically with the transmitted signal and the reference voltage, thus further reducing signaling margin.
Yet another source of noise results from the non-uniform impedance presented by the signal return current. That is, in contrast to a differential signaling approach in which the signal current flowing on a given conductor is typically matched by a reverse flow on a parallel, counterpart conductor, the signal return current in single-ended system 100 is split between the ground and VDD rails, 109 and 107. More specifically, as shown by the AC current-flow diagram at 122, the signal return current, iRET, is typically forced to flow through external and internal bypass capacitors (111 and 113, respectively) in order to return from ground rail 109 to VDD rail 107 and thus may not easily be maintained parallel to the signal line 105. Consequently, a non-uniform impedance (i.e., one or more impedance discontinuities) is presented to a signal propagating on the signal line 105, thus producing reflections and transients that constitute yet another source of margin-reducing noise.